Some Integrated Circuits (IC), such as memory devices, generate clock signals using Adaptive Delay-Locked Loop (ADLL) circuitry. ADLLs are useful, for example, for generating clock signals in a manner that is insensitive to Process, Voltage and Temperature (PVT) variations.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.